Axion-HDL

User Guide

  • Getting Started
    • Installation
      • Prerequisites
    • Quick Start
      • Step 1: Define Registers
      • Step 2: Generate Output
      • Step 3: Check Generated Files
      • Step 4: Integrate
    • Next Steps
  • Data Formats
    • Format Overview
    • Module-Level Attributes
      • VHDL (@axion_def)
      • SystemVerilog (@axion_def)
      • YAML/TOML/XML/JSON
      • VHDL Module Attributes Table
    • Register-Level Attributes
      • Access Modes
      • Complete Attribute Reference
        • VHDL Register Attributes (@axion)
        • SystemVerilog Register Attributes (@axion)
        • YAML Register Attributes
        • XML Register Attributes
        • JSON Register Attributes
        • TOML Register Attributes
    • Advanced Features
      • Clock Domain Crossing (CDC)
      • Strobe Signals
      • Subregisters (Packed Fields)
      • Advanced Subregister Features
        • Auto-Packing
        • Default Value Aggregation
        • Strobe Aggregation
        • Mixed Access Modes
        • Overlap Handling
      • Wide Signals (>32 bits)
      • Default Values
      • Manual Address Assignment
    • Format Comparison
    • Quick Reference Card
      • VHDL Annotation Syntax
      • SystemVerilog Annotation Syntax
      • YAML Structure
      • XML Structure
      • JSON Structure
      • TOML Structure
    • Enumerated Values (enum_values)
      • VHDL Annotation
      • SystemVerilog Annotation
      • YAML
      • JSON
      • TOML
      • XML (Simple, Nested)
      • XML (SPIRIT)
    • Hierarchy File Format
      • Top-Level Structure
      • Instance Entry Fields
      • YAML
      • TOML
      • JSON
      • XML
      • Output Naming Rules
  • Examples
    • SystemVerilog Example: Audio Processor
    • VHDL Example: SPI Master
    • YAML Example: LED Blinker
    • XML Example: PWM Controller
    • JSON Example: GPIO Controller
    • TOML Example: SPI Master
    • Generated Output Files Summary
    • Golden Model Example
  • Outputs
    • Output Summary
    • VHDL Register Module
      • Entity Structure
      • Features
      • Port Directions by Access Mode
      • Typed AXI Ports (axion_common_pkg)
    • SystemVerilog Register Module
      • Module Structure
      • Key Features
      • Typed AXI Ports (axion_common_pkg)
    • C Header File
      • Contents
      • Macro Naming Convention
    • Documentation Outputs
      • Markdown (register_map.md)
      • HTML (<module>.html, index.html)
    • Re-exportable Formats
      • YAML Output (<module>_regs.yaml)
      • JSON Output (<module>_regs.json)
      • XML Output (<module>_regs.xml)
      • Python Register Model (<module>_regs.py)
    • Generation Control
      • CLI Flags
      • Example Commands
    • Output Directory Structure
    • Integration Examples
      • Vivado IP Integrator
      • Embedded C Development
      • Documentation Workflow
    • Enumerated Values in Outputs
      • Docs (Markdown/HTML/PDF)
      • C Header
      • YAML / JSON Export
      • XML (SPIRIT) Export
      • VHDL Package (*_regs_pkg.vhd)
      • SystemVerilog Package (*_regs_pkg.sv)
    • Address Map Report (Hierarchy Mode)
      • Table Columns
      • Example

Usage Modes

  • Command Line Interface (CLI)
    • Installation
    • Basic Usage
    • Quick Start
    • Command Reference
      • Source Options
      • Output Options
      • Generation Flags
      • GUI Options
      • Information Options
    • Complete Workflow Examples
      • 1. Single Module Generation
      • 2. Multi-Module Project
      • 3. SystemVerilog Module
    • CI/CD Integration
      • GitHub Actions
      • GitLab CI
      • Makefile Integration
      • Shell Script
    • Configuration File
    • Supported File Types
    • Exit Codes
    • Tips
  • Python API
    • Installation
    • Quick Start
    • Core Class: AxionHDL
      • Creating an Instance
      • Adding Sources
      • Excluding Files
      • Analysis
      • Generation
    • Complete Examples
      • Example 1: Basic Generation
      • Example 2: Multi-Source Project
      • Example 3: Custom Workflow with Validation
      • Example 4: Address Overlap Detection
      • Example 5: Selective Generation
      • Example 6: Build System Integration
    • RuleChecker API
      • Check Categories
    • Data Structures
      • Module Structure
      • Register Structure
    • Error Handling
    • CI/CD Integration
      • GitHub Actions with Python
      • GitLab CI with Python
      • Pytest Integration
      • Pre-commit Hook
      • Custom Build Script
      • Example 7: SystemVerilog Project
    • Python Register Model API
      • Getting a model from AxionHDL
      • AxionHDL model methods
      • RegisterSpaceModel
      • RegisterModel
      • FieldModel
      • Exceptions
      • Generating *_regs.py files
    • See Also
  • Interactive GUI
    • Installation
    • Starting the GUI
      • Basic Launch
      • With Source Files
      • Custom Port
    • Dashboard
      • Statistics Cards
      • Module Cards
      • Empty State
    • Module Editor
      • Module Properties
      • Register Table
      • Register Actions
      • Validation
    • Diff & Review
      • Views
      • Actions
      • Color Coding
    • Output Generation
      • Output Directory
      • Format Toggles
      • Generation Process
      • Activity Log
    • Rule Check
      • Running Checks
      • Check Categories
      • Results Display
      • Summary
    • Configuration
      • Source Management
      • Exclude Patterns
      • Settings
      • Apply Changes
    • Configuration File (.axion_conf)
      • File Format (JSON)
      • Behavior
    • Navigation
      • Navbar Links
      • Breadcrumbs
    • Keyboard Shortcuts
    • Unsaved Changes
    • Troubleshooting
      • Flask Not Found
      • Port Already in Use
      • Browser Doesn’t Open
      • Changes Not Saving
    • File Modification Behavior
  • Rule Checker
    • Running Rule Check
      • CLI
      • GUI
      • Python API
    • Check Categories
      • Address Overlap Detection
      • Address Alignment
      • Naming Convention
      • Reserved Keywords
      • Style Guide
      • Duplicate Names
      • Duplicate Module Names
      • Invalid Default Values
      • Missing Documentation
      • Format Issues
        • JSON/YAML Issues
        • XML Issues
      • Register Attribute Validation
      • Parse Errors
      • Subregister Overlap
      • Logical Integrity
    • Report Formats
      • Text Report
      • JSON Report
    • Integration with CI/CD
      • Exit Codes
      • Example GitHub Actions
      • Example Makefile
    • Suppressing Warnings
    • VHDL Reserved Words Reference

Reference

  • Requirements
    • Requirements Documents
      • Core Requirements
        • Requirement Categories
        • 1. Core Protocol (AXION)
        • 2. Bus Protocol (AXI-LITE)
        • 3. VHDL Parsing (PARSER)
        • 4. Code Generation (GEN)
        • 5. Error Handling (ERR)
        • 6. Command Line Interface (CLI)
        • 7. Clock Domain Crossing (CDC)
        • 8. Address Management (ADDR)
        • 9. Stress Testing (STRESS)
        • 10. Subregisters (SUB)
        • 11. Default Values (DEF)
        • 12. Validation & Diagnostics (VAL)
        • 13. XML Input (XML-INPUT)
        • 14. YAML Input (YAML-INPUT)
        • 15. SystemVerilog Generation (SV-GEN)
        • 16. Enumerated Values Requirements
        • Typed AXI Ports (AXION-TYPES)
        • 18. Hierarchy File Support (HIER)
        • 20. Python Register Model (REG-MODEL)
      • GUI Requirements
        • Requirement Categories
        • 1. Server Launch (GUI-LAUNCH)
        • 2. Dashboard (GUI-DASH)
        • 3. Module Editor (GUI-EDIT)
        • 4. Save & Unsaved Changes (GUI-SAVE)
        • 5. File Modification (GUI-MOD)
        • 6. Output Generation (GUI-GEN)
        • 7. Rule Check (GUI-RULE)
        • 8. Diff & Review (GUI-DIFF)
        • 9. Navigation & Layout (GUI-NAV)
    • Core Requirements Overview
    • GUI Requirements Overview
    • Test Mapping
      • Python Unit Tests
      • VHDL Simulation Tests
      • GUI Tests
    • Requirement Format
      • Example
    • Adding New Requirements
  • Developer Guide
    • Project Structure
    • Development Setup
      • Prerequisites
      • Installation
    • Running Tests
      • All Tests
      • Python Unit Tests
      • VHDL Simulation Tests
      • GUI Tests (Playwright)
    • Branching Workflow
      • Feature Development
      • Releases
    • Code Style
      • Python
      • Linting
    • Adding New Features
      • 1. Check Requirements
      • 2. Add Requirement
      • 3. Write Tests First
      • 4. Implement Feature
      • 5. Run Tests
      • 6. Update Documentation
    • Building Documentation
      • Local Build
      • ReadTheDocs
    • Useful Make Targets
  • API Reference
    • Core Classes
      • AxionHDL
        • Constructor
        • Source Management Methods
        • Exclusion Methods
        • Analysis Methods
        • Generation Methods
        • Validation Methods
    • RuleChecker
      • Methods
      • Return Value
      • Check Categories
    • Parsers
      • VHDLParser
      • SystemVerilogParser
      • YAMLInputParser
      • JSONInputParser
      • XMLInputParser
      • TOMLInputParser
    • Generators
      • VHDLGenerator
      • SystemVerilogGenerator
      • DocGenerator
      • CHeaderGenerator
      • XMLGenerator
      • YAMLGenerator
      • JSONGenerator
      • TOMLGenerator
    • Data Structures
      • Module Dictionary
      • Register Dictionary
      • Register Fields
    • Exceptions
      • AddressConflictError
    • See Also
Axion-HDL
  • Search

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